A 24 V brushless-drive board came back from a customer site with consistently higher than calculated output ripple on its 12 V logic rail. The design used six 10 µF X7R MLCCs in 0603, rated 16 V, in parallel. Incoming inspection had passed the whole batch at 10.1–10.4 µF at 1 kHz with no DC bias. The ripple measured in the field was roughly 2.5 times the calculated value, and the customer suspected counterfeit ceramics.
The parts were genuine X7R, RoHS-declared and within tolerance for every datasheet parameter at zero bias. The initial suspects were counterfeit ceramic. The actual cause was a sizing and verification gap: nobody had checked the capacitance at the working DC voltage. This is the DC-bias effect, and it is normal, measurable and preventable.
Class 2 Dielectrics Lose Permittivity under DC Bias
X5R and X7R classify as Class 2 dielectrics based on ferroelectric barium titanate. A DC field aligns the ferroelectric domains, which lowers the effective permittivity of the ceramic. The drop grows with field strength, so a part operated near its rated voltage retains far less capacitance than the same part operated at a fraction of its rating. This loss is invisible to a zero-bias LCR measurement, which is why it does not show up in a normal incoming inspection.
Two parameters dominate the retention: the voltage headroom and the chip geometry. A 0603 16 V part loaded at 12 V sits at 75% of its rating; typical retention in that condition is roughly 55–70% of the zero-bias value. The same dielectric and case size rated 50 V and loaded at 12 V sits at 24% of rating and typically retains above 85%.
| Bias level, % of rated DC voltage | Typical retained capacitance, 0603 X5R/X7R | Typical retained capacitance, 0805/1210 X5R/X7R | Checkpoint |
|---|---|---|---|
| 20% | 90–95% | 95–98% | No practical concern |
| 50% | 75–85% | 85–92% | Most boards operate here; confirm in design |
| 75% | 55–70% | 70–80% | Review before finalizing a decoupling rail |
| 90% | 45–60% | 60–75% | Avoid for bias-critical positions |
These ranges are indicative for typical production ceramics, not a substitute for the vendor curve. X5R formulations generally sit near the lower edge of each range; X7R sits near the middle; C0G (NP0) shows no DC-bias loss at all.
Root-Cause Checks, in Order
- Measure the actual bias. Put a DSO probe with a 10× setting on each MLCC terminal while the board runs at maximum load. Many designs apply a higher voltage than the nominal rail during startup or transient load steps.
- Confirm the dielectric class. If the part is X7R, X5R or a similar Class 2 type, DC-bias loss is expected. If the design claims to use C0G and the marking shows a Class 2 code, that is a real substitution problem.
- Compare case size and voltage rating to the design intent. A smaller case size or a lower rated voltage for the same nominal capacitance usually means thinner dielectric layers and a steeper bias curve.
- Request the vendor curve. The resistance to DC-bias loss varies between manufacturers and even between formulations of the same series. The curve is the reference for every acceptance decision.
Measuring Capacitance under DC Bias
An LCR meter with a built-in DC-bias source is the direct tool. Set the frequency to 1 kHz and the AC level to 1 Vrms, a common reference condition for MLCC capacitance measurement. Sweep the bias from 0 V to the intended operating voltage and record C(bias)/C(0V) at each step. If the meter has no bias source, a bias tee that couples the DC offset while isolating the AC measurement path works the same way.
Acceptance values for a sourcing decision:
- The zero-bias capacitance must be within ±20% of the nominal value; this confirms the part itself is in tolerance.
- At the operating bias, the ratio C(bias)/C(0V) should be within ±10 percentage points of the vendor’s typical curve.
- If no curve is available, use a rough gate: a 16 V part at 12 V should retain at least 50%; a 25 V part at 12 V should retain at least 70%. Reject parts that fall below these thresholds for bias-critical positions.
Document the measured ratio in the incoming inspection report. A part that fails the bias test will also fail in the field regardless of its zero-bias value.
Prevention Checklist for Procurement and Design
- State the operating DC voltage in the RFQ, not only the rated voltage, so the supplier can match a part with adequate headroom.
- Ask the supplier to provide the DC-bias curve and the RoHS/REACH declaration before order placement.
- Buy a small sample lot for bias verification when a new series or vendor is introduced; scaling can follow the bias test result.
- Check MOQ flexibility, because bias-critical rails often need a higher voltage rating than the rest of the board, and holding two ratings in stock is the normal solution.
- For signal-level decoupling positions below roughly 1 µF, consider C0G where bias stability is more important than capacitance density.
- Add the DC-bias measurement to the incoming inspection plan for any rail where ripple or hold-up time is a design constraint.
DC-bias loss is not a defect; it is a property of the material. What becomes a defect is an unverified substitution, a missing curve, or an inspection that stops at zero bias. A supplier that stocks parts with documented bias data and can ship them with consistent lead time makes the inspection step shorter and the failure mode less likely.
